(1) Field of the Invention
The present invention relates to semiconductor devices in general, and more particularly, to a method of forming shallow trench isolation without corner leakage effects.
(2) Description of the Related Art
Trench structures in semiconductors are employed for various purposes, such as for replacement of LOCOS (local oxidation of silicon) isolation for like devices within the same tub in a CMOS device, or for isolation of n-channel from p-channel devices, or as trench-capacitor structures in DRAMS, or for isolation of bipolar devices. Shallow refilled trenches are used primarily for isolating devices of the same type, and trench-capacitor structures are normally fabricated with narrow, deep trenches. By virtue of the shape of a trench, there usually results a sharp corner or shoulder where the trench intersects with the surface within which the trench is formed. Consequently, concentration of the electric-field occurs at the sharp corner region which in turn causes the lowering of the threshold voltage of the corner region, and this part of the device turns on at a lower voltage than does the interior portion of the device. As is known in the art, the problem is exacerbated if there is a downward step in the field oxide adjacent the trench. The larger the step, the lower the threshold voltage, and unwanted subthreshold conduction begins at progressively lower values of the gate voltage. It is disclosed later in the embodiments of this invention a method of eliminating these common but undesirable steps at the trench corners and shoulders.
In prior art, several techniques have been developed to minimize the parasitic leakage caused by the electricfiled concentration at the trench corner. Because the trench corner can be made sharper by successive process steps during manufacturing, one approach is to protect the corner from the effects of subsequent processes.
Mandelman, et al., in U.S. Pat. No. 5,521,422 uses a corner dielectric co-aligned with the trench corner extending a subminimum dimension distance from the corner. The corner dielectric serves as a spacer and is formed as shown in FIGS. 1a-1f. In FIG. 1a, a silicon substrate (10) is provided with pad oxide (20) and nitride surface coating (30). Window (40) with nearly vertical sidewall (35) is photolithographically defined in surface coating (30) and oxide layer (20) as shown in FIG. 1b. Trench (45) is etched, defined by window (40) as illustrated in FIG. 1c. It will be noted that now the intersection of oxide layer (20) and trench (45) forms trench corner (17). Trench (45) and window (40) are then filled with insulator (50). Insulator (50) is then polished, stopping on surface coating (30) (not shown). Then surface coating (30) is removed leaving insulator (50) with nearly vertical sidewalls (55) extending above the surface (13) of silicon substrate (10) as shown in FIG. 1d. It will be known by those skilled in the art that during isotropic etches used in standard semiconductor processing after trench (45) is filled with insulator (50), trench corner (17) becomes exposed. During the commonly used wet-etch process, sidewall (55) retreats to (53) while a groove-like recess (51) is formed, as shown by broken lines in FIG. 1d. In other words, corner (17) becomes sharpened further and hence more susceptible to electric-field concentration. In order to avoid this, Mandelman, et al., provide spacer (60) self-aligned to sidewall (55) of insulator (50) by performing standard process of depositing a spacer insulator having a desired thickness and then directionally etching to selectively remove the spacer insulator from horizontal surfaces as shown in FIG. 1e. Finally, gate dielectric (70) is formed by conventional processing, gate conductor (80) deposited and photolithographically defined. Thus, gate conductor (80) is spaced from corner (17) by corner dielectric (60) and the electric field in the corner region is significantly reduced.
In another approach, Barden in U.S. Pat. No. 4,760,034 discloses a method for forming a DRAM cell having a capacitor adjacent a field effect transistor (FET), wherein the FET fabrication area is protected from adverse effects of the capacitor formation. Barden accomplishes this by forming edge-sealed multi-layer structure while protecting adjacent region by screen oxide layer.
Lur of U.S. Pat. No. 5,395,790, on the other hand, discloses a method of partial trench etching to form at least one narrow trench, followed by anneal-treatment to release stress and eliminate crystalline defects, therein. Isolating material is then filled into the narrow trench to form a complete stress-free isolation layer.
An improved LOCOS device isolation method for forming a field oxide is disclosed by Nguyen, et al., in U.S. Pat. No. 4,897,364. In one embodiment of the invention a silicon substrate is provided having a pad oxide formed on its surface and a first polysilicon stress-relief buffer layer formed overlying the first polysilicon layer. Next, a second polysilicon, etch-resistant buffer layer is deposited overlying the first nitride layer. The first nitride layer and second polysilicon layer are patterned by conventional lithography while the fist polysilicon and pad oxide layers remained unpatterned. A second nitride layer is deposited overlying the patterned second polysilicon layer and exposed regions of the first polysilicon layer. Sidewalls are formed on the edges of the patterned first nitride and second polysilicon layers by anisotropically etching the second nitride layer using the first and second polysilicon layers as etching endpoints. Finally, the field oxide is grown by conventional methods. The grown field oxide exhibits reduced the well-known bird's beak length, and the resulting field separation is not limited by optical lithography resolution.
In still another approach, Liao teaches in U.S. Pat. No. 5,652,162, a method for forming field-oxide regions for a ROM (read-only-memory) cell where channels with concave shapes are formed to increase the effective channel length of the device.
In the present invention, a method is described where the integrity of the trench corner is protected from unwanted process induced alterations by using pad oxide as a screen oxide and by eliminating the wet etching of the trench oxide.